KELEFOURAS, Vasilios; KERAMIDAS, Georgios; VOROS, Nikolaos. In: VLSI (ISVLSI), 2017 IEEE Computer Society Annual Symposium on. IEEE, 2017. S. 477-482.
In this paper, we present a new methodology that provides i) a theoretical analysis of the two most commonly used approaches for effective shared cache management (i.e., cache partitioning and loop tiling) and ii) a unified framework to fine tuning those two mechanisms in tandem (not separately). Our approach manages to lower the number of main memory accesses by one order of magnitude keeping at the same time the number of arithmetical/addressing instructions in a minimal level.We also present a search space exploration analysis where our proposal is able to offer a vast deduction in the required search space.